Floorplanning in VLSI, Explained
Floorplanning is the first real physical step in the backend, and it is the one that decides whether the rest of the flow is easy or miserable. It is where you define the shape of the block, place the big macros, plan the power, and set the stage for placement and routing. Get it right and everything downstream goes smoothly. Get it wrong and you fight congestion and timing for weeks.
What you actually decide
- The die and core area, and the gap between them for IO and the power ring
- Where the hard macros (memories, IP) sit
- Utilization, how full the core is with standard cells
- The power plan: rings, straps, and the standard-cell rails
- Placement blockages and macro halos that reserve space
Utilization and aspect ratio
Utilization is the fraction of the core area taken by cells. Too low wastes area, too high leaves the placer no room and congestion explodes. Aspect ratio is the shape of the core. A near-square block is usually easiest to route, while a long thin block stretches paths and hurts timing.
| Choice | If too low | If too high |
|---|---|---|
| Utilization | Wasted area and power | Congestion, placement fails |
| Macro spacing | Wasted area | No room for routing and PDN |
Placing the macros
Macros are placed by how data flows, not by habit. Blocks that talk to each other go near each other, and macros are pushed to the edges so they do not block routing across the core. Each macro gets a halo, a keep-out region, so standard cells and the router have room near its pins.
Power planning happens here
The power grid is built during floorplanning, not after. Rings surround the core, straps cross it on the upper metals, and rails feed the standard-cell rows. Planning power early is how you avoid IR-drop surprises that otherwise appear after placement, when fixing them is expensive.
Run an early trial placement or global route to see congestion before you commit the floorplan. A floorplan that looks clean to the eye can still route terribly. Catching it now is free, catching it after CTS is not.
Do not treat floorplanning as a quick setup step to rush through. More backend problems start here than anywhere else. The hour you spend on a good floorplan saves days of timing and congestion debugging later.
Key takeaways
- Floorplanning sets die and core area, macro placement, utilization, and power
- Place macros by dataflow and keep them out of the routing path
- Build the power grid during floorplanning to avoid late IR-drop surprises
- Validate with early congestion analysis before moving on