Physical Design Interview Questions and Answers
These are the physical design questions that come up again and again in interviews, with the kind of answers a working engineer would give. Read each one, then close it and say the answer in your own words. The goal is to explain the concept clearly, not to recite a definition.
Walk me through the physical design flow
From a synthesized netlist: floorplanning (die and core, macro placement, power plan), placement of standard cells, clock tree synthesis, routing (global then detailed), and signoff (timing, physical verification, IR drop). Each stage feeds the next, and problems in an early stage show up as pain in a later one.
What is utilization, and what happens if it is too high
Utilization is the fraction of the core area filled by cells. Too high and the placer has no room to spread cells, so congestion explodes and timing fails. Too low wastes area and power. You start comfortable and tighten as the flow proves clean.
What is skew, and is it always bad
Skew is the difference in clock arrival time between two flops. It is not always bad. Useful skew intentionally delays a capture clock to give a tight setup path more time. The catch is that the same skew tightens hold on that path and shifts the budget downstream.
Why do hold violations appear after CTS
Before CTS the clock is ideal, so skew is zero and hold numbers are fiction. CTS introduces real skew, and that is exactly what creates hold violations. This is why you never close hold before the clock tree is built.
How do you fix congestion
First find where it comes from, because congestion is usually created upstream in the floorplan or placement. Fixes include lowering utilization in the hot region, improving macro placement and channels, adding placement blockages, and spreading cells. Changing router settings rarely fixes a real congestion problem.
What is IR drop and how do you reduce it
IR drop is the voltage lost across the power network resistance, so cells see less than the full supply and slow down. Dynamic IR drop, from many cells switching at once, is the dangerous kind. You reduce it with a stronger power grid, decap cells near hot spots, and by spreading high-activity logic.
What is the antenna effect
During manufacturing, a long metal wire connected to a gate can accumulate charge from plasma etching and damage the thin gate oxide. The router fixes it by inserting antenna diodes or by jumping the net to another layer to break up the long segment.
What is the difference between DRC and LVS
DRC, design rule check, verifies the layout obeys the foundry manufacturing rules, like spacing and width. LVS, layout versus schematic, verifies the layout actually matches the intended netlist. DRC asks can this be built, LVS asks is this the right thing.
In every PD interview answer, add the why and one consequence. Do not just define utilization, say what too high does to congestion. That single habit makes you sound like an engineer who has run the flow, not someone who read about it.
Key takeaways
- Know the flow end to end and how each stage affects the next
- Be ready to explain utilization, skew, CTS, congestion, IR drop, and antenna
- Always pair a definition with its cause and consequence
- Speak from the flow, not from a textbook