STA5 min read

What is Hold Time in VLSI?

Hold time is the second timing requirement of a flip-flop, and it is the one that should worry you more than setup. It is the minimum time that data must stay stable after the clock edge for the captured value to be safe.

The definition

When the clock edge captures data, the value being stored needs a moment to settle inside the flop. Hold time is the window after the edge during which the data input must not change. If new data races in too soon, it corrupts the value that was just captured.

The hold equation

Hold is checked against the same clock edge that captured the data, not the next one. The condition that must hold:

text
Tcq + Tlogic_min  >=  Thold + Tskew

Tcq        = clock-to-Q of the launching flop
Tlogic_min = shortest combinational delay between flops
Thold      = hold time of the capturing flop
Tskew      = capture-clock arrival minus launch-clock arrival

Notice what is missing: the clock period. Hold does not depend on Tclk at all, which is the single most important fact about it.

Why hold is scarier than setup

Because hold is independent of the clock period, you cannot slow the clock to escape it. If a hold violation reaches silicon, the chip is simply broken at that path, at any frequency. That is why hold is signed off at the fast process corner, where cells are quickest and the data race is tightest.

How hold violations are fixed

  • Add buffers or delay cells on the fast path to slow the data
  • Increase the short-path logic delay where possible
  • Manage clock skew so capture does not arrive too late relative to launch
Watch out

Hold fixes add delay cells, and that delay eats into setup margin on the same path. On a tight path you can trade a hold violation for a setup one. Always re-check setup after fixing hold.

Pro Tip

The senior-level answer in an interview is this: hold violations are unrecoverable on silicon because you cannot slow the clock to escape them, which is why hold is closed after CTS at the fast corner. Say that and you have separated yourself from someone who only memorized the definition.

Key takeaways

  • Hold time is the window after the clock edge where data must stay stable
  • A hold violation means data arrived too fast on a short path
  • Hold is independent of the clock period, so a slower clock cannot fix it
  • It is signed off at the fast corner and fixed with delay cells
Have a question about this? Ask in the community.