Scan Design

Scan is the single most important DFT technique. It solves the controllability and observability problem in one stroke by turning every flip-flop in the design into something you can directly load and read.

The core idea

Normally the flip-flops deep inside a chip are almost impossible to set to a known state or observe from outside. Scan replaces each ordinary flop with a scan flop that has a small multiplexer in front of it. In normal mode the flop works exactly as before. In test mode, all the scan flops are connected into one or more long shift registers called scan chains.

The scan flop

A scan flop is a regular flop plus a mux on its data input. A control signal, scan enable, selects which input the flop captures.

• scan_enable = 0: the flop takes its normal functional data (functional mode).
• scan_enable = 1: the flop takes the scan input, the output of the previous flop in the chain (shift mode).

How a scan test runs

1. Shift in: with scan enable high, clock the chain to load a known test pattern into every flop.
2. Capture: set scan enable low for one functional clock so the flops capture the response of the combinational logic.
3. Shift out: raise scan enable again and clock the chain to read out the captured response, while shifting the next pattern in.
4. Compare the shifted-out values against the expected response to find defects.

Because you can load any value into every flop and read back every flop, you have made the entire design both fully controllable and fully observable. That is why scan gives such high coverage.

Scan chains

The flops are stitched into chains, each with a scan-in pin and a scan-out pin. Designs use many parallel chains rather than one giant one, because the longest chain sets how many cycles each pattern takes to shift. Balancing chain lengths keeps test time down.