Preface | VLSI Physical Design | SiliconPath

Foundations

Digital Electronics
Verilog
Hardware Protocols
Design Verification
Clock Domain Crossing

Backend (RTL to GDSII)

Synthesis
Physical Design
Static Timing Analysis
Physical Verification
Low Power
Design for Test

Tools & Career

TCL for EDA
Linux for VLSI
Interview Q&A
STA Interview Q&A
Career Roadmap

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OpenLane RTL-to-GDS
Interview Bootcamp
Fresher Pack
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Preface

Front matter

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VLSI and physical design education for chip engineers in India.

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Design & Verification

Digital Electronics
Verilog
Design Verification
Clock Domain Crossing
Hardware Protocols

Physical Design

Synthesis
Physical Design
Static Timing Analysis
Physical Verification
Low Power Design & UPF
Design for Test

Career & Tools

Interview Q&A
Career Roadmap
TCL for EDA
Linux for VLSI

Courses

OpenLane RTL-to-GDS
Interview Bootcamp
Fresher Pack
Resume Tips
The Book (e-book)

Company

About
Contact
Blog
Community

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