Module 39 min

SystemVerilog for Verification

The data types and features that make testbenches powerful

Designs are written in Verilog or SystemVerilog. Testbenches use the richer features of SystemVerilog - the parts built specifically for verification. You do not need all of it at once; here are the pieces you will use constantly.

logic - the type to default to

In testbenches, just use logic for almost everything. It replaces the old wire vs reg headache - logic can be driven both ways, so you stop worrying about which to pick.

Containers that grow

Type	What it is	Everyday use
Fixed array	A row of slots with a set size	A small lookup table
Dynamic array	An array you resize at run time	Buffer of unknown length
Queue	A line you push to and pop from	A model of a FIFO or a to-do list of expected results
Associative array	A lookup by any key, like a dictionary	Sparse memory, scoreboards

systemverilog

int   q[$];          // a queue
q.push_back(5);      // add to the end
q.push_back(9);
int x = q.pop_front(); // take from the front -> 5

int mem[int];        // associative array (dictionary)
mem[1000] = 42;      // store 42 at address 1000

Tasks and functions

function - returns a value, takes no time (no delays). Use for calculations like an expected result.
task - can consume time (delays, waits). Use for sequences of actions like "drive this, wait a clock, drive that."

Interfaces - bundle the wires

Instead of passing a dozen separate signals everywhere, an interface bundles related wires into one named group. It keeps connections clean as the design grows, and it is the standard way testbenches connect to a DUT.

systemverilog

interface bus_if (input logic clk);
  logic        valid;
  logic [7:0]  data;
endinterface

// Now a whole bus is passed as one thing, not 3 signals.

Pro tip

Reach for queues constantly in verification. When the DUT produces results, you push the expected value into a queue, and pop it to compare when the real result arrives. That simple push/pop pattern is the backbone of a scoreboard, which you meet later in this path.

Watch out

SystemVerilog is large. Do not try to memorize it all. Learn logic, arrays, queues, tasks, and functions first - that is enough to write strong testbenches. Add the rest as specific needs come up.