Digital Electronics - Interview Q&A

Top questions asked in VLSI, embedded, and hardware design interviews covering digital fundamentals.

Q1. What is the difference between a latch and a flip-flop?

Latch is level-sensitive: it is transparent (passes input to output) while the enable signal is HIGH. Output can change any time during the enable window.

Flip-Flop is edge-triggered: it samples input only at the clock edge (rising or falling) and holds that value until the next edge. Output changes only once per clock cycle.

In synchronous VLSI design, flip-flops are preferred because they prevent glitch propagation and give predictable timing. Latches are avoided in most RTL because synthesis tools may not handle them correctly - a missing else in a combinational always block infers an unintended latch.

Q2. Why is NAND a universal gate? Prove it.

A gate is universal if it can implement NOT, AND, and OR - the three primitive gates needed to build any Boolean function.

NOT from NAND: Y = (A·A)' = A' - connect both inputs together. AND from NAND: AND = NOT(NAND) = ((A·B)')' = A·B - NAND followed by a NAND-as-NOT. OR from NAND: By De Morgan's: A+B = (A'·B')' = NAND(NOT(A), NOT(B)) - invert both inputs then NAND.

Since we can build NOT, AND, OR using only NAND gates, NAND can implement any Boolean function. Same logic applies for NOR.

Q3. What is 2's complement and why is it used?

2's complement is the standard method for representing signed (positive and negative) integers in binary hardware.

How to compute: Invert all bits, then add 1. Example: −6 in 4-bit → +6 = 0110 → invert = 1001 → add 1 = 1010

Why it's used: 1. Single representation of zero (unlike sign-magnitude which has +0 and −0). 2. Subtraction reduces to addition: A−B = A + (2's complement of B). This means hardware needs only an adder - no separate subtractor circuit. 3. Overflow detection is straightforward: overflow occurs when carry-in ≠ carry-out of the MSB.

All modern CPUs and VLSI ALUs use 2's complement arithmetic.

Q4. What is a race condition in sequential circuits?

A race condition occurs when two signals that should arrive simultaneously (or in a specific order) arrive at different times due to unequal propagation delays, causing incorrect circuit behavior.

Critical race: The final state of the circuit depends on which signal arrives first - leading to non-deterministic behavior. Example: in an SR latch, if S and R both go LOW at nearly the same time after being HIGH, the final state (Q=0 or Q=1) depends on propagation delays.

Non-critical race: Multiple state variables change, but regardless of the order, the circuit always reaches the same final stable state.

How to avoid: Use synchronous design with a single clock. Edge-triggered flip-flops eliminate races within one clock domain by providing a definite sampling moment.

Q5. Explain setup time and hold time with respect to a D flip-flop.

Setup Time (tsu): Minimum time the D input must be stable before the active clock edge. The flip-flop's internal circuitry needs this time to pre-charge and prepare for the sampling operation.

Hold Time (th): Minimum time the D input must remain stable after the active clock edge. Needed because the internal latch takes time to fully capture the value after the clock arrives.

Setup Violation: D changes too close to clock edge. The FF may enter a metastable state - output oscillates for an unpredictable time before settling. Fix: reduce clock frequency, reduce combinational path delay.

Hold Violation: D changes too soon after clock edge. More dangerous - cannot be fixed by slowing the clock. Fix: add delay buffers on the data path. Hold violations cause functional failure in silicon.

Q6. What is metastability in digital circuits?

Metastability is a condition where a flip-flop's output is in an undefined intermediate state (neither 0 nor 1) for a period of time, before eventually resolving to a valid logic level.

When it occurs: When the setup or hold time of a flip-flop is violated - most commonly at clock domain crossing (CDC) boundaries where asynchronous signals are captured.

Why it's a problem: Different parts of the circuit may see different resolved values. The resolution time is theoretically unbounded - in rare cases, the output stays metastable long enough to cause system failures.

How to mitigate: Use 2-flop synchronizers (two cascaded D-FFs on the receiving clock domain). The first FF may go metastable, but gives a full clock cycle to resolve. The second FF then sees a stable value with very high probability. For critical applications, 3-flop synchronizers are used.

Q7. What is the difference between Moore and Mealy FSMs?

Moore FSM: Output depends only on the current state. Outputs are registered (synchronous) and change only on clock edges. More states may be needed. Outputs are glitch-free.

Mealy FSM: Output depends on both the current state AND current inputs. Outputs are combinational and can change immediately when inputs change. Fewer states needed. Outputs can glitch if inputs glitch.

In practice: Moore FSMs are safer and preferred in synchronous VLSI designs where output glitches could cause problems downstream. Mealy FSMs are used when a faster response to inputs is needed and the downstream logic can tolerate combinational outputs.

In Verilog, Moore outputs are typically in a separate always @(state) block; Mealy outputs are in the always @(state or input) next-state block.

Q8. What is a K-map and why is it used?

A Karnaugh Map (K-map) is a graphical method for simplifying Boolean expressions by visually identifying groups of adjacent 1s in a truth table laid out in Gray code order.

Why it's used: Boolean algebra simplification is tedious and error-prone for expressions with many variables. K-maps provide a systematic, visual approach that guarantees a minimal sum-of-products (SOP) or product-of-sums (POS) expression.

Practical limit: K-maps are practical for up to 4–5 variables. Beyond that, Quine-McCluskey algorithm or synthesis tools are used.

In VLSI context: Logic synthesis tools like Design Compiler and Genus automate Boolean minimization using algorithms derived from these concepts. Understanding K-maps helps you predict and verify synthesis results.

Q9. Implement a D flip-flop using JK flip-flops. What is excitation table?

An excitation table tells you what inputs a flip-flop needs to make a desired state transition. It is the inverse of the characteristic table.

JK excitation table: Q(t)=0 → Q(t+1)=0: J=0, K=X (don't care) Q(t)=0 → Q(t+1)=1: J=1, K=X Q(t)=1 → Q(t+1)=0: J=X, K=1 Q(t)=1 → Q(t+1)=1: J=X, K=0

D FF using JK: For a D FF, Q(t+1) = D. Using JK excitation: When D=0: need Q→0, so J=0, K=X → K=1, J=0 → J=D, K=D' When D=1: need Q→1, so J=1, K=X → K=0, J=1 → J=D, K=D' Result: J = D, K = D' - connect D directly to J and D' (inverted) to K.

Q10. What is a ripple counter and what are its limitations?

A ripple counter (asynchronous counter) is built by cascading T or JK flip-flops where the Q output of each stage drives the clock of the next stage.

How it works: LSB FF toggles every clock cycle. MSB FFs toggle when the previous stage transitions from 1→0 (or 0→1 for up/down). Carry "ripples" from LSB to MSB.

Limitations: 1. Propagation delay accumulates: Total delay = n × tFF. For 8-bit counter at 28nm, this could be hundreds of picoseconds - limits maximum frequency. 2. Glitch states: Intermediate invalid states exist during transitions (e.g., 0111→0110→0100→0000 before reaching 1000). These cause false decoding outputs. 3. Not synchronous: Cannot be safely used in synchronous designs - the output bits are not all valid at the same clock edge.

Solution: Synchronous counters - all FFs share the same clock; carry is computed combinationally.

Q11. Explain fan-in and fan-out in logic gates.

Fan-in: The number of inputs a gate can handle. A 4-input AND gate has fan-in of 4. Increasing fan-in increases gate delay and area (more transistors). In practice, fan-in is typically limited to 4–5 in standard cells.

Fan-out: The number of gate inputs a single gate output can drive. Driving too many loads increases the capacitance on the output net, which increases delay (RC delay) and can degrade signal integrity.

In VLSI: Synthesis tools report max fan-out violations. The fix is to buffer high fan-out nets - insert buffers to split the load. Clock nets have extremely high fan-out (drives thousands of FFs) and require dedicated clock tree buffers with high drive strength.

Q12. What is a multiplexer? How do you implement a Boolean function using a MUX?

A multiplexer (MUX) is a combinational circuit that selects one of 2n data inputs and routes it to the output, based on an n-bit select signal.

Implementation of Boolean function using MUX: To implement an n-variable function: use a 2n-1:1 MUX. Connect (n-1) variables to the select lines. For each combination of select values, connect the data input to either 0, 1, or the nth variable (or its complement) based on the truth table rows it covers.

Example - F(A,B,C) using 4:1 MUX with A,B as select: S1S0=AB=00: rows where A=0,B=0 → check C dependence → wire I0 = C (or constant) S1S0=AB=01: rows where A=0,B=1 → wire I1 S1S0=AB=10: rows where A=1,B=0 → wire I2 S1S0=AB=11: rows where A=1,B=1 → wire I3

This is the same principle used in FPGA Look-Up Tables (LUTs).

Q13. What is the difference between synchronous and asynchronous reset?

Synchronous Reset: The flip-flop resets to 0 only at the active clock edge when reset=1. Verilog: always @(posedge clk) if (rst) Q <= 0; else Q <= D; Pros: No glitch on reset, predictable timing, treated like any other data path. Cons: Reset must be held long enough to be seen by the clock edge. Longer reset assertion required.

Asynchronous Reset: The FF resets immediately when reset asserts, independent of the clock. Verilog: always @(posedge clk or posedge rst) if (rst) Q <= 0; else Q <= D; Pros: Instant reset, no waiting for clock edge. Works even if clock is stopped. Cons: Reset deassertion (going from 1→0) can cause metastability if it happens close to the clock edge. Asynchronous reset release needs synchronization.

Industry practice: Asynchronous assert, synchronous de-assert (ADSD) - best of both worlds.

Q14. What is propagation delay and how does it affect maximum operating frequency?

Propagation delay (tp): Time for a logic gate's output to respond to a change in input. Measured as the time from input crossing 50% VDD to output crossing 50% VDD.

tpHL: Delay for output to go from HIGH to LOW. tpLH: Delay for output to go from LOW to HIGH. Propagation delay = (tpHL + tpLH) / 2

Maximum operating frequency: In a clocked system, the clock period must be long enough for: Tclk ≥ tCQ + tcombo + tsu where tCQ = clock-to-Q delay of launching FF, tcombo = combinational path delay, tsu = setup time of capturing FF.

Fmax = 1 / Tclk,min

The combinational path with the largest total delay is the critical path. Reducing critical path delay increases Fmax.

Q15. What is a priority encoder and where is it used?

A priority encoder accepts multiple input lines and encodes the position of the highest-priority active input into a binary output. It also generates a Valid (V) output that goes HIGH when any input is active.

Example - 4:2 Priority Encoder (I3 has highest priority): If I3=1: output = 11 (regardless of I0,I1,I2) If I3=0, I2=1: output = 10 If I3=0, I2=0, I1=1: output = 01 If I3=0, I2=0, I1=0, I0=1: output = 00 If all inputs = 0: V=0 (no valid input)

Real-world applications: 1. Interrupt controllers (PIC, APIC): When multiple devices request CPU attention simultaneously, the priority encoder selects the highest-priority interrupt to service first. 2. Arbiters in buses: Multiple bus masters competing for access - highest priority wins. 3. Cache and TLB replacement: Priority logic selects which entry to evict.