Sequential Logic Circuits
Latch vs Flip-Flop - Critical Distinction
What Makes a Circuit "Sequential"? — Sequential circuits have memory - the output depends on both current inputs AND past history (current state). They contain feedback or storage elements (latches, flip-flops). Every register, counter, FSM, CPU, and memory cell is sequential. This is the foundation of all stateful digital design.
Latch vs Flip-Flop - Critical Distinction
Latch (Level-Sensitive)
Output changes as long as the enable (E or G) signal is HIGH - it is transparent while enabled. No clock edge required.
Problem: If input glitches while enabled, glitch passes through to output. Creates timing hazards in synchronous designs. Called "transparent latch" or "D latch".
Flip-Flop (Edge-Triggered)
Output changes only at the clock edge (rising or falling). Samples input at that instant and holds it until the next edge.
Advantage: Immune to input glitches between clock edges. All modern synchronous digital designs use edge-triggered flip-flops. This is why setup and hold time matter.
SR Latch (NAND & NOR Based)
NOR-based SR Latch
| S | R | Q (next) | State |
|---|---|---|---|
| 0 | 0 | Q (hold) | Memory |
| 0 | 1 | 0 | Reset |
| 1 | 0 | 1 | Set |
| 1 | 1 | Invalid | Forbidden |
NAND-based SR Latch (Active LOW)
| S̄ | R̄ | Q | State |
|---|---|---|---|
| 1 | 1 | Q (hold) | Memory |
| 1 | 0 | 0 | Reset |
| 0 | 1 | 1 | Set |
| 0 | 0 | Invalid | Forbidden |
The Four Flip-Flops
| Flip-Flop | Inputs | Characteristic Equation | Behavior | Use Case |
|---|---|---|---|---|
| D (Data) | D | Q(t+1) = D | Stores D at clock edge. Output follows input with one-cycle delay. | Registers, pipeline stages, all modern synchronous designs |
| JK | J, K | Q(t+1) = JQ' + K'Q | J=K=0: hold | J=0,K=1: reset | J=1,K=0: set | J=K=1: toggle. No invalid state. | Counters, more versatile than SR. Legacy designs. |
| T (Toggle) | T | Q(t+1) = T⊕Q | T=0: hold current state | T=1: toggle (complement Q) | Counters - chain T-FFs with T=1 for a ripple counter |
| SR | S, R | Q(t+1) = S + R'Q | Set, Reset, Hold. S=R=1 is forbidden. | Rarely used directly; basis for understanding latches |
D Flip-Flop is King in VLSI — In modern synchronous VLSI design, essentially all sequential elements are D flip-flops. JK and T flip-flops require more transistors and create timing complexity. Synthesis tools always map sequential behavior to D-FFs from the standard cell library. When you write always @(posedge clk) in Verilog, the synthesizer infers D flip-flops.
Setup Time & Hold Time - Why They Matter
Setup Time (tsu)
The minimum time the data input (D) must be stable before the clock edge arrives. If data changes too close to the clock edge, the FF may not correctly capture the value → setup violation.
Hold Time (th)
The minimum time data must remain stable after the clock edge. If data changes too soon after the clock, the captured value may be corrupted → hold violation. Hold violations are harder to fix than setup violations.
Registers & Shift Registers
A register is a group of D flip-flops sharing a common clock. An n-bit register stores n bits of data in parallel.
| Shift Register Type | Data In | Data Out | Use Case |
|---|---|---|---|
| SISO (Serial In, Serial Out) | 1 bit/cycle | 1 bit/cycle | Delay line, serial communication |
| SIPO (Serial In, Parallel Out) | 1 bit/cycle | n bits at once | Serial-to-parallel conversion (SPI, UART) |
| PISO (Parallel In, Serial Out) | n bits at once | 1 bit/cycle | Parallel-to-serial conversion |
| PIPO (Parallel In, Parallel Out) | n bits at once | n bits at once | General-purpose register, pipeline buffer |
Counters
Asynchronous (Ripple) Counter
Each FF clock is driven by Q of the previous FF. Simple but slow - carry ripples through all stages. Delay = n × tFF
Problem: Intermediate glitch states exist - e.g., going from 0111→1000, you may see 0110, 0100, 0000 briefly. Cannot be used reliably in synchronous designs.
Synchronous Counter
All FFs share the same clock. Carry logic is computed combinationally in advance. All bits change simultaneously. No glitch states. Used in all modern digital designs.
4-bit synchronous up counter counts: 0000→0001→…→1111→0000 (modulo-16).
Ring Counter & Johnson Counter — Ring Counter: Shift register with output fed back to input. Only one FF is HIGH at any time. N FFs → N states. Used for sequencing. Johnson Counter (Twisted Ring): Q' (complemented output) fed back to input. N FFs → 2N states. Cleaner Gray-code-like transitions, used in frequency dividers.
Interactive Waveform Lab
Toggle signals, animate the timeline, and inject a setup or hold violation to see exactly how it appears on a real CLK / D / Q waveform.