Physical Design Interview Questions (Top 30)

1. What is utilization in floorplanning and what is a good target value?

Utilization = (Total Standard Cell Area) / (Core Area) × 100%. It represents how densely cells are packed in the core.

Target: 60–75% for most designs. Lower (<50%) wastes die area and increases cost. Higher (>80%) causes routing congestion, difficulty placing buffers, and degraded routability. Memory-heavy designs may use 40–60% because large SRAMs occupy significant area.

2. What is the difference between die area and core area?

Die area: The total silicon area of the chip, including the I/O ring, pads, and all structures to the edge of the die.

Core area: The interior region where standard cells and macros are placed. It is surrounded by the I/O ring. Core area = Die area − I/O ring area − margins.

The core-to-die margin accommodates power rings, I/O pad connections, and design rule keepouts. Utilization is measured relative to the core area, not die area.

3. What is IR drop and how does it affect the design?

IR drop is the voltage reduction along the power delivery network due to resistive metal wires. V_drop = I × R.

Effects:

• Cells receiving lower VDD switch slower → increased cell delay → potential setup violations

• Severe IR drop can prevent cells from switching at all → functional failure

• Dynamic IR drop (transient) from simultaneous switching of many cells

Fix: Wider power stripes, more vias, adding decap cells near the IR hotspot, reducing switching current by spreading cells.

4. What is electromigration (EM) and how do you fix it?

Electromigration (EM) is the gradual displacement of metal atoms in a wire due to electron momentum transfer at high current densities. Over time it creates voids (opens) or hillocks (shorts), causing chip failure.

Fix:

• Widen the wire to reduce current density (J = I/A)

• Add parallel wires (increase cross-section)

• Add more vias (reduce via current density)

• Reduce switching frequency or activity

EM analysis is part of sign-off using tools like Voltus or RedHawk.

5. What is clock skew? What is acceptable skew?

Clock skew = difference in clock arrival time between any two flip-flops in the design (or between launch FF and capture FF on a specific path).

Skew = T_clk_capture − T_clk_launch

Acceptable values:

• Local skew (adjacent FFs): < 30–50 ps

• Global skew (across chip): < 100–200 ps

Positive skew (capture FF's clock arrives later): relaxes setup, tightens hold. Negative skew: tightens setup, relaxes hold. CTS targets balanced (near-zero) skew between all FFs in a domain.

6. What is the difference between global routing and detailed routing?

Global Routing: Divides the chip into a coarse grid (GCells) and assigns each net to a sequence of GCells. Determines which metal layers and routing regions each net passes through. Fast, approximate - does not produce actual wire geometries. Identifies congested areas.

Detailed Routing: Works within the global routing assignment to produce exact wire coordinates, widths, vias, and layer assignments. Must satisfy all DRC rules. The actual GDSII-ready metal geometries are the output.

7. What is a DRC violation? Give three examples.

DRC (Design Rule Check) violations are layout patterns that violate foundry manufacturing rules:

• Spacing violation: Two wires on the same metal layer are closer than the minimum spacing rule

• Width violation: A wire is narrower than the minimum width for that metal layer

• Via enclosure violation: Metal doesn't extend enough beyond the via in all directions

• Antenna violation: Metal attached to gate has too high area ratio (damages oxide during fab)

• Density violation: Metal fill percentage outside foundry-specified min/max range

8. What is LVS and what errors does it catch?

LVS (Layout vs. Schematic) extracts a netlist from the physical layout (by identifying connected metal regions as nets and transistors from poly-over-active patterns) and compares it to the reference schematic/netlist.

Errors caught:

• Open circuits: A connection exists in schematic but is missing/broken in layout

• Short circuits: Two nets that should be separate are connected in layout

• Extra devices: Layout has transistors not in schematic

• Missing devices: Schematic has cells not present in layout

LVS must be clean before tape-out.

9. What is a macro in physical design? How is it placed?

A macro is a large pre-designed block (hard macro) with a fixed layout: SRAM, ROM, PLL, analog IP, large memories. Unlike standard cells which are placed in rows, macros have fixed dimensions and internal structure.

Macro placement guidelines:

• Place at die edges or corners to minimize routing blockage in the center

• Align to row boundaries if possible

• Add a "halo" or keepout around each macro (no std cells within 2–5µm)

• Consider macro pin accessibility - pins should face the routing channels

• Group related macros (e.g., all SRAMs near their controllers)

10. What are filler cells and their purpose?

Filler cells (decap fillers) are placed in empty spaces between standard cells in each row to:

• Maintain N-well continuity across the row (required for correct transistor operation)

• Connect power rails (VDD/VSS straps run through standard cell rows)

• Provide decoupling capacitance (some filler cells include capacitors)

• Ensure minimum density requirements for metal layers

Different sizes exist (FILL1, FILL2, FILL4, FILL8, FILL16, FILL32) and the placer fills every gap. Must be removed before ECO changes and re-inserted after.

11. What is an antenna violation in routing?

During plasma etching in semiconductor fabrication, metal wires connected to gate terminals accumulate charge. If the metal-to-gate area ratio exceeds a threshold, the charge can damage the thin gate oxide.

Antenna ratio = Metal area connected to gate / Gate oxide area

Fixes:

• Jump up to higher metal layer (top layer is added last, less exposure)

• Insert antenna diodes at gate inputs (discharge the accumulated charge)

• Use antenna-aware routing (route to higher layer early)

Antenna violations are found by DRC and must be fixed before tape-out.

12. What is crosstalk and how does it affect timing?

Crosstalk occurs when a switching wire (aggressor) capacitively couples noise onto an adjacent wire (victim).

Timing impact:

• Crosstalk delta delay: Aggressor switching in same direction as victim → speeds up victim (improves setup, worsens hold). Opposite direction → slows down victim (worsens setup).

• Crosstalk noise/glitch: On a quiet net, coupling from aggressor creates a voltage spike that may cause a logic error if the net is near a switching threshold.

Fixes: Shield critical nets with VDD/VSS, widen wire spacing, use lower metal layers (smaller coupling cap).

13. What is the difference between legalization and detailed placement?

Legalization: After global placement places cells at approximate (possibly overlapping) locations, legalization moves each cell to the nearest legal position - aligned to a placement row, on the power rail grid, with no overlaps. Cells may move significantly from their global placement position.

Detailed Placement: After legalization, cells are in legal positions but timing may be degraded. Detailed placement does local cell swaps, single-row and multi-row moves to improve timing and reduce wirelength while maintaining legality.

14. What is a placement blockage? Name three types.

A placement blockage prevents the placer from placing standard cells in a specified area.

Types:

• Hard blockage: No cells placed at all. Used around macros, analog circuits, special structures.

• Soft blockage: Discourages placement but allows it if necessary for congestion relief.

• Partial blockage: Only buffers and inverters (low-level cells) allowed - commonly used around macro halos.

• Route blockage: Blocks routing (not placement) on specific metal layers in a region.

15. What is SPEF? Why is it needed for sign-off timing?

SPEF (Standard Parasitic Exchange Format) is a file that describes the extracted RC parasitics (resistance and capacitance) of every wire in the physical layout. After routing, an extraction tool (like StarRC or RCX) reads the physical layout and produces SPEF.

SPEF is needed because wire delays depend heavily on actual metal resistance and capacitance, which are only known after physical layout. Pre-route timing uses estimated wire loads (WLM) which can be 20–30% off. Sign-off STA uses SPEF for accurate, real timing. Without SPEF, timing sign-off is unreliable.

16. What is timing-driven placement?

Timing-driven placement considers timing criticality when placing cells. Critical path cells are placed close together to minimize wire length and thus wire delay. Non-critical paths can tolerate longer wires.

The placer uses early wire length estimation and constraint data to prioritize cell proximity for critical nets. Without timing-driven placement, a pure wirelength minimizer might spread critical cells apart, degrading timing after routing when actual wire RC is seen. Most modern placers (Innovus, ICC2) do timing-driven placement by default.

17. What is a power domain and what is level shifting?

A power domain is a region of the chip that operates at a specific supply voltage, potentially different from the rest of the chip. Used in low-power design to run non-critical blocks at lower voltage (lower power).

Level shifters are required when a signal crosses between two power domains at different voltages. They translate signal levels: a signal valid at 0.6V/1.2V in domain A must be converted to the 0.8V/1.8V levels of domain B. Without level shifters, the receiver sees incorrect logic levels, causing functional failure. Level shifters must be inserted in the netlist during synthesis/PD with proper UPF (Unified Power Format) flow.

18. What is the purpose of tap cells in physical design?

Tap cells (also called well taps) connect the N-well to VDD and substrate to VSS at regular intervals to prevent latchup. They have no active function but provide necessary bias connections.

Without tap cells, parasitic PNP/NPN transistors in the CMOS structure can turn on, creating a low-resistance path from VDD to VSS (latchup), permanently damaging the chip. Foundry rules specify maximum tap cell pitch (typically 20–50µm). They are placed in every standard cell row at regular intervals.

19. What is congestion in routing? How do you resolve it?

Congestion occurs when the number of wires that need to pass through a routing region exceeds the available routing tracks (routing overflow).

Fixes:

• Reduce placement density (lower utilization) in congested areas

• Add routing blockages on congested layers to force rerouting

• Move macros to open routing channels

• Add extra metal layers via process upgrades

• Use high-fanout net synthesis to break up congested drivers

• Adjust floorplan to redistribute logic

Congestion map analysis in Innovus/ICC2 shows hotspots before detailed routing.

20. What is double patterning and why is it needed?

At advanced nodes (<20nm), the minimum wire pitch required is smaller than what a single photolithography exposure can resolve. Double patterning splits the layout into two separate masks, each printed in a separate exposure, whose combined result achieves the fine pitch.

This requires the layout to be "colorable" - adjacent wires must be assigned to different masks (colors). DRC checks for double patterning conflicts (two adjacent same-color wires that should be different colors). Routing tools must be double-patterning-aware and ensure no conflicts.

21. What is a flyline (ratsnest) and how is it used?

A flyline (ratsnest) is a straight-line visual connection between unconnected pins that are logically connected in the netlist. It shows the router "intent" - which pins must be connected - before actual routing is done.

Uses:

• Visual guide during floorplanning to estimate wire congestion and length

• Identify poor floorplan choices (macros creating long flylines across the chip)

• Estimate wirelength for timing budgeting

High-density flyline areas after floorplanning predict routing congestion hot spots. Move macros/cells to reduce crossing flylines.

22. What is a high-fanout net and how is it handled in PD?

A high-fanout net is a signal connected to a very large number of sink pins (e.g., enable, scan_en, reset driving hundreds or thousands of FFs). High fanout causes:

• Excessive wire capacitance → slow transition → timing violation

• Single wire spanning entire chip → routing congestion

Handling: Use buffer tree synthesis - insert buffers to split the net into sub-nets. The synthesis and PD tools do this automatically for nets exceeding max_fanout. Scan enable and test signals often need 4–6 levels of buffering.

23. What is the difference between ICC2 and Innovus?

Both are industry-leading place-and-route tools from different vendors:

Synopsys ICC2: Tightly integrated with DC (write_icc2), PrimeTime for timing sign-off, and IC Validator for DRC. Uses hierarchical database (.dlib).

Cadence Innovus: Tight integration with Genus (write_db/read_db), Tempus for in-design STA, and Calibre in-design. Known for Concurrent Optimization (CCOpt) for CTS.

Both support advanced features (multi-patterning, advanced node DRC, power analysis). Choice depends on existing tool stack and foundry PDK support.

24. What is a power intent file (UPF/CPF)?

UPF (Unified Power Format) and CPF (Common Power Format) describe the power architecture of a multi-voltage design:

• Power domain definitions (which cells are in each domain)

• Supply voltages for each domain

• Power state definitions (ON, OFF, low-power)

• Level shifter and isolation cell requirements

• Power switching cell locations

UPF is now IEEE 1801 standard. The PD tool reads UPF to automatically insert level shifters, isolation cells, and power switches at domain boundaries. Without UPF, multi-voltage designs cannot be correctly implemented.

25. What is the difference between CTS and CTO?

CTS (Clock Tree Synthesis): Builds the clock distribution network from scratch - inserting buffers, inverters, and routing wires to distribute the clock to all FFs with controlled skew and latency.

CTO (Clock Tree Optimization): A post-CTS step that fine-tunes the existing clock tree - adjusting buffer sizes, changing net routes, and tweaking the tree topology to improve skew, latency, and clock power without fully rebuilding the tree. Used after post-route optimization when incremental clock improvement is needed. In Innovus: ccopt_design covers both CTS and CTO.

26. What is metal fill and why is it required?

Metal fill is dummy metal patterns inserted into empty areas of each metal layer to satisfy foundry density rules. CMP (Chemical Mechanical Polishing) during fabrication requires uniform metal density across the wafer to achieve planar surface topography.

Without adequate fill: CMP removes too much metal in sparse areas (dishing) or leaves too much in dense areas (erosion) → non-uniform heights → via formation failures → reliability problems.

Fill is inserted after routing using fill tools. It must not electrically connect to any signal but must meet min/max density rules on each layer within specified check windows.

27. What is the difference between pre-route and post-route optimization?

Pre-route optimization occurs before detailed routing. Wire delays are estimated (using virtual wire models). Cell placement, sizing, and buffering changes are fast because no DRC checking is needed. Timing closure is attempted here first for efficiency.

Post-route optimization uses actual extracted parasitics (RC from real wires). It is slower and must maintain DRC cleanliness with every change. Changes are limited (ECO-mode: only add/resize buffers/inverters, minimal perturbation to avoid DRC). Sign-off timing happens post-route.

28. What is a standard cell row? How does orientation affect placement?

A standard cell row is a horizontal strip in the core area with fixed height (matching the standard cell height for the technology node). Rows alternate between N-side up (N2HS) and P-side up, with power rails (VDD and VSS) running horizontally through them. All standard cells must snap to row boundaries.

Row orientation alternates (flipped in Y) so adjacent rows share power rails, reducing the number of power straps needed. Some cells can only be placed in certain orientations (e.g., cells with specific Nwell connections). Placement tools handle orientation automatically per-row.

29. What happens during sign-off? What must pass before tape-out?

Sign-off is the final verification phase before releasing the design to the foundry. All checks must pass with zero failures:

• STA: Zero setup AND hold violations across all MMMC corners

• DRC: Zero design rule violations (Calibre DRC clean)

• LVS: Layout vs. Schematic clean (zero shorts/opens)

• IR Drop: All cells receive sufficient voltage (static + dynamic)

• EM: All metal/via segments below current density limits

• Antenna: All gates meet antenna ratio rules

• ESD: ESD protection structures verified

30. What is the purpose of decap cells?

Decap cells (decoupling capacitor cells) are standard-cell-height structures that contain a large capacitor between VDD and VSS. They serve as local charge reservoirs:

• Supply instantaneous current to switching cells without waiting for current from the power pads (which have long RC path)

• Reduce dynamic IR drop by providing local charge

• Filter high-frequency noise on the power supply

Placed in empty spaces near high-switching-activity areas. Some filler cells also contain small decap capacitances. Excessive decap can cause excessive inrush current at power-on.