Synthesis Interview Questions (Top 30)

1. What is logic synthesis and what are its inputs and outputs?

Logic synthesis is the process of converting an RTL (Register Transfer Level) hardware description into a gate-level netlist optimized for a target technology.

Inputs: RTL code (Verilog/VHDL/SystemVerilog), technology library (.lib/.db), timing constraints (.sdc), design rules. Outputs: Gate-level netlist (.v), mapped SDC, timing/area/power reports, DDC database.

2. What is the difference between compile and compile_ultra in Design Compiler?

compile: Standard compile with basic optimization. Limited effort. Options: -map_effort [low/medium/high], -incremental for re-optimization of existing netlist.

compile_ultra: Advanced optimization including retiming, adaptive body biasing, path-based analysis. Enables -no_autoungroup (prevents flattening) and -timing_high_effort_script. Significantly better QoR at the cost of longer runtime. Used in production flows.

3. What is a technology library (.lib file)? What does it contain?

A .lib (Liberty) file characterizes every standard cell in the technology at specific PVT conditions. It contains:

• Cell delay tables (input transition vs output load)

• Setup/hold times for sequential cells

• Leakage and dynamic power values

• Area in technology units

• Pin capacitances, max fanout, max transition limits

• Function description (Boolean)

Multiple .lib files cover different PVT corners (ss125c, tt25c, ff-40c).

4. What is a false path? Give an example of when you would use set_false_path.

False path: A timing path that exists in the netlist but is not functionally active - it will never carry real data during operation, so timing should not be analyzed on it.

Examples:

• Asynchronous reset/set ports: set_false_path -from [get_ports rst_n]

• Scan test mode paths (active only during test, not functional operation)

• Paths between mutually exclusive clocks that never switch simultaneously

• Configuration pins written once at startup

Note: Incorrectly setting false paths can hide real timing problems. Use with care.

5. What is a multicycle path? How is set_multicycle_path used?

A multicycle path is one that is intentionally designed to take more than one clock cycle to propagate. This relaxes the timing constraint on that path.

Example: A multiplier that takes 2 clock cycles: set_multicycle_path 2 -setup -from [get_cells mult_inst/reg*] set_multicycle_path 1 -hold -from [get_cells mult_inst/reg*]

The -hold must be explicitly set to (N-1) to avoid hold violations introduced by the relaxed setup. Failure to set hold correction is a very common bug.

6. What is clock gating and why is it used?

Clock gating reduces dynamic power by stopping the clock to a flip-flop or a group of flip-flops when their output is not needed. Instead of clocking an FF every cycle (wasting power toggling), a gating condition (enable signal) controls whether the clock reaches the FF.

Implementation: Synthesis tools insert ICG (Integrated Clock Gating) cells which are AND/OR-latch combinations that suppress the clock edge cleanly without glitches. Reduces dynamic power by 20–40% in typical designs.

7. What is the difference between WNS, TNS, and WHS?

WNS (Worst Negative Slack): The most negative setup slack in the design. Represents the single worst timing path. Must be ≥ 0 at sign-off.

TNS (Total Negative Slack): Sum of all negative slacks across all endpoints. Indicates the total amount of timing work needed. WNS=0 but TNS<0 means many marginal paths.

WHS (Worst Hold Slack): The most negative hold slack. Indicates the worst hold violation. Must also be ≥ 0. Fixed by inserting delay buffers on short paths.

8. What is retiming in synthesis?

Retiming moves registers (flip-flops) across combinational logic boundaries without changing the circuit's functional behavior. It balances pipeline stages to improve frequency.

Example: If Stage 1 has 3ns of logic and Stage 2 has 1ns, retiming moves a register to equalize ~2ns each, doubling achievable frequency. The tool handles the mathematical transformation automatically. Enabled via compile_ultra in DC.

9. What is operand isolation in power optimization?

Operand isolation prevents switching activity on functional units (like adders, multipliers) when their outputs are not being used. An AND gate or mux is inserted at the inputs of the datapath block, driven by the enable signal. When disabled, all inputs are forced to 0, preventing glitches from propagating through the combinational logic and reducing switching power significantly.

10. What happens during elaboration in synthesis?

Elaboration parses the HDL source files and builds an internal design representation (GTECH netlist - technology-independent generic gates). During elaboration:

• Module hierarchy is constructed

• Parameters/generics are resolved to constants

• FSMs are identified and optionally encoded

• Registers, memories, operators (+, *, >>) are mapped to GTECH primitives

• Design rule checks (unconnected ports, latches vs FFs) are performed

The check_design command after elaboration reports any issues.

11. What is set_dont_touch and when do you use it?

set_dont_touch prevents DC from optimizing, resizing, or removing a specific cell or net. Use cases:

• Protect manually sized critical cells from being downsized

• Preserve specific clock buffers needed for DFT

• Protect cells needed for post-silicon debug/observation points

• Guard hand-placed analog boundary interface cells

Over-use of set_dont_touch can degrade QoR by blocking legitimate optimizations.

12. What is the difference between target_library and link_library?

target_library: The technology library whose cells DC will USE when mapping the design. These are the cells that appear in the output netlist.

link_library: Libraries used to RESOLVE module references during linking. Includes "*" (current design) + all .db files. Needed so DC can find instantiated sub-modules and external IPs. A cell can be in link_library but not target_library - it gets resolved but DC won't use it for new cells.

13. What is ungroup and when should you use it during synthesis?

ungroup flattens a sub-module into its parent, removing the hierarchical boundary. This allows DC to optimize logic across that boundary (e.g., constant propagation from parent into child, logic sharing between siblings).

Use when: Sub-module boundaries prevent critical optimization. In compile_ultra, the -no_autoungroup flag disables DC's automatic ungrouping. Manual ungrouping is done before compile: ungroup -all -flatten. Tradeoff: loses hierarchy for debug and incremental compile benefits.

14. What is scan insertion and how does synthesis handle it?

Scan insertion (Design for Test, DFT) replaces regular flip-flops with scan flip-flops (SFF) that have an additional scan data input (SI) and scan enable (SE). During test mode, all SFFs form a chain allowing external test patterns to be shifted in and captured results shifted out.

In synthesis: After compile, insert_dft and preview_dft commands handle scan. The SDC must set false paths on scan paths (set_false_path -from [get_ports scan_en]). Scan adds ~5–10% area overhead.

15. What is the significance of set_max_area 0 in DC?

set_max_area 0 tells Design Compiler to minimize area as much as possible (target = 0 means "minimize"). DC will aggressively use smaller cells, share logic, and apply area recovery techniques after meeting timing. Setting this to 0 doesn't mean area will be 0 - it's a directive to minimize. Without this command, DC may leave unused area if timing is met. Always set after timing constraints are applied so timing takes priority.

16. What are HVT, SVT, and LVT cells? How are they used in synthesis?

Multi-threshold voltage cells on the same process node:

LVT (Low Vt): Fast switching, but high leakage. Used on critical timing paths. SVT (Standard Vt): Balanced. General use cells. HVT (High Vt): Slow, but very low leakage. Used on non-critical paths to reduce standby power.

Strategy: Use LVT to fix WNS on critical paths; replace non-critical LVT cells with HVT to recover power. DC can perform multi-Vt optimization automatically when multiple .lib corners are provided.

17. What is GTECH in Design Compiler?

GTECH (Generic Technology) is Synopsys's internal, technology-independent logic library used as an intermediate representation during synthesis. After elaboration, the design is mapped to GTECH primitives (GTECH_AND2, GTECH_FD1, etc.) before technology mapping to the target library. GTECH allows Boolean optimization without technology-specific constraints. The check_design on a GTECH netlist catches structural issues before committing to technology mapping.

18. What is the purpose of set_clock_uncertainty?

set_clock_uncertainty adds a timing margin to account for:

• Jitter: Cycle-to-cycle variation in clock edge arrival (PLL jitter)

• Skew: Spatial variation in clock arrival (before CTS; post-CTS uses propagated clocks)

• Margin: Extra guardband for post-silicon variation

Pre-CTS: set_clock_uncertainty models all uncertainty. Post-CTS: Usually only jitter+margin, as skew is captured in propagated clock latencies. Setup and hold have separate uncertainty values.

19. What is path grouping in synthesis optimization?

Path grouping organizes timing paths into groups so DC can apply targeted optimization effort. Each group can receive different weights and effort. Default groups: REGOUT (reg-to-output), REGIN (input-to-reg), COMBO (combinational), and per-clock groups.

group_path -name critical_paths -critical_range 0.5 -weight 5

Higher weight = more optimization effort. Useful to tell DC to focus on specific paths without spending runtime on already-met paths.

20. What is the difference between read_verilog and analyze + elaborate?

read_verilog: Reads, analyzes, and elaborates the design in one step. Simpler for single-design flows.

analyze + elaborate (two-step): analyze -format verilog -library WORK [file list] elaborate top_module

The two-step approach is preferred for large hierarchical designs because analyze compiles each file to an intermediate form, and elaborate builds the hierarchy. This allows reuse of analyzed modules and better error isolation. Also enables explicit parameter override during elaborate.

21. What causes latch inference vs flip-flop inference in synthesis?

In Verilog RTL: Flip-flop is inferred when: output is assigned only on a clock edge (always @(posedge clk)). Latch is inferred when: output is assigned inside a level-sensitive always block AND not all conditions assign the output (incomplete if/case).

Example latch inference: always @(en or d) if (en) q = d; // q holds when en=0 → LATCH

Latches are generally undesirable in synthesis (timing hard to analyze). Fix: Use flip-flops with explicit reset, or make if/case statements complete with else/default.

22. What is incremental compile and when do you use it?

Incremental compile (compile -incremental) re-optimizes only the portions of the design that violate constraints, leaving already-met portions unchanged. It is faster than a full compile and is used:

• After making small ECO changes to the netlist

• After constraint changes affecting only a subset of paths

• In a second-pass optimization after an initial compile

Not as thorough as a full compile_ultra - use only when runtime is critical or changes are known to be local.

23. What does check_timing report and why is it important?

check_timing validates that all paths in the design are covered by timing constraints. It reports:

• Unconstrained paths: Flip-flops or ports with no clock or timing constraint → timing not analyzed → potential sign-off risk

• Loops: Combinational loops (no register) which cause infinite path delays

• No-clock endpoints: FFs without an associated clock

Always run check_timing before reporting timing. "Clean" means 0 warnings - every path is constrained.

24. What is propagated clock vs ideal clock in synthesis?

Ideal clock: Clock arrives at all FFs simultaneously with zero skew and zero network delay. Used pre-CTS. The set_clock_uncertainty models expected skew/jitter as a guardband.

Propagated clock: After CTS, the actual clock network delay is computed from the clock source through every buffer/inverter to each FF's clock pin. The tool uses real propagated delays - more accurate, removes pessimism of ideal clock uncertainty. set_propagated_clock [all_clocks] switches to propagated mode in PrimeTime post-CTS.

25. What is set_driving_cell and set_load?

set_driving_cell: Specifies the cell driving each input port, allowing DC to accurately compute input transition times. Without this, DC assumes an ideal (zero-resistance) driver. Example: set_driving_cell -lib_cell BUFX4 [get_ports data_in*]

set_load: Specifies the capacitive load on output ports (models the off-chip load). Example: set_load 0.05 [get_ports data_out*]

Both are necessary for accurate I/O timing analysis. Without them, input/output timing will be optimistic.

26. What is the SAIF file and how is it used in power analysis?

SAIF (Switching Activity Interchange Format) captures the toggle rate and static probability of every net in the design from simulation. It is used by synthesis and power analysis tools to compute accurate dynamic (switching) power rather than relying on default activity assumptions (typically 20% toggle rate).

Flow: Run RTL or gate-level simulation → dump SAIF → read in DC/PT for power analysis: read_saif -input sim.saif -instance top. More accurate switching data = more accurate power optimization decisions.

27. What is the difference between a latch and a flip-flop from a timing perspective?

Flip-flop (edge-triggered): Captures data only at the clock edge. Setup/hold times apply at that edge. STA treats it as a fixed timing endpoint - straightforward.

Latch (level-sensitive): Transparent when clock is high (or low). Data can "time-borrow" through the latch during the transparent phase, borrowing time from the next cycle. This makes STA significantly more complex - the tool must perform "time-borrowing" analysis. Latches in pipelines can improve throughput but require careful constraint handling with set_latch_time and cycle_time constraints.

28. What is a generated clock? Give an example.

A generated clock is a clock derived from a master clock by division, multiplication, or phase shift - typically from a PLL output or a clock divider register.

create_generated_clock -name CLK_DIV2 -source [get_ports clk_in] -divide_by 2 [get_pins clkdiv_reg/Q]

Generated clocks are essential for STA to correctly analyze paths crossing from the master to generated domain. Without declaring them, those paths are unconstrained. Generated clocks also inherit uncertainty from their master unless explicitly overridden.

29. What is a combinational loop and how does it affect synthesis?

A combinational loop is a circuit path where the output feeds back to its own input without any register (flip-flop/latch) in between. This creates infinite path delay in STA (the propagation loops forever), and in real hardware causes oscillation or lock-up states.

Synthesis tools detect loops via check_design and report them as errors. Loops must be fixed before synthesis can complete. Common causes: feedback mux without enable register, asynchronous handshake signals coded incorrectly in RTL.

30. What is register balancing vs pipeline optimization?

Register balancing (retiming): Moves existing registers within the current pipeline structure to equalize logic depth between stages. No new registers are added. The functional latency (number of cycles) stays the same.

Pipeline optimization: Adds NEW pipeline stages (registers) to reduce combinational depth at the cost of increased latency. This is an architectural decision made at RTL level, not done automatically by synthesis.

Key difference: Retiming is synthesis-level; pipelining is architectural. Both improve timing but retiming is transparent to function while pipelining increases output latency.