Module 59 min

VLSI Glossary

Term	Definition
AOCV	Advanced On-Chip Variation. OCV derating method that applies smaller derating to longer (higher cell count) paths due to statistical averaging.
Antenna Violation	Layout violation where cumulative metal area connected to a gate exceeds the foundry's antenna ratio limit, risking gate oxide damage during plasma etching.
AOCV	Advanced OCV - path-depth-aware derating that reduces pessimism vs flat OCV for long paths with many cells (statistical averaging effect).
Aspect Ratio	Core height divided by core width. Typically 1:1 (square) but can vary based on I/O and macro constraints.
Back-Annotation	Loading post-layout extracted parasitics (SPEF) into STA for accurate timing analysis using real wire RC values.
Blackbox	A module whose internal implementation is hidden from synthesis/STA. Only the timing model (liberty file) is used for analysis.
Buffer Tree	A hierarchy of buffers used to drive high-fanout nets, reducing wire capacitance per driver and improving transition times.
CCD	Concurrent Clock and Data optimization in Cadence CTS flow - simultaneously optimizes clock tree and data paths.
CDC	Clock Domain Crossing. Transfer of signals between flip-flops clocked by different, potentially asynchronous clocks. Requires synchronizer circuits to prevent metastability.
Metastability	A state where a flip-flop output remains at an indeterminate voltage level after violating setup or hold time. The output will eventually resolve to 0 or 1 but after an unpredictable delay. Probability of prolonged metastability decreases exponentially with resolution time.
MTBF	Mean Time Between Failures (for synchronizers). The average time before a metastability event causes a system failure. Increases exponentially with the resolution time given to the synchronizer. A 2-FF synchronizer has orders-of-magnitude better MTBF than a 1-FF synchronizer.
Latch Borrowing	Also called time borrowing. A technique using level-sensitive latches where a slow pipeline stage borrows timing slack from the following faster stage. The latch remains transparent past its nominal closing time. Maximum borrow = half the clock period.
Async FIFO	Asynchronous First-In First-Out buffer with separate read and write clock domains. Read/write pointers are encoded in Gray code so they can be safely synchronized across clock domains using 2-FF synchronizers. Used for multi-bit data crossing between clock domains.
Gray Code	Binary encoding where only one bit changes between consecutive values (e.g., 00→01→11→10). Used in async FIFO pointers so that only one bit needs to cross clock domains at a time - metastability on one bit causes at most ±1 count error, not data corruption.
CMP	Chemical Mechanical Polishing. Fab step that planarizes the wafer surface after each metal layer deposition. Requires uniform metal density.
CRPR	Clock Reconvergence Pessimism Removal. Removes double-counting of OCV derating on the shared clock path between launch and capture FFs.
CTS	Clock Tree Synthesis. Process of building the clock distribution network to minimize skew and control latency from clock source to all FF clock pins.
CK-to-Q	Clock-to-Q propagation delay of a flip-flop - time from clock edge to Q output settling to new value. Part of data path delay.
Compile Ultra	Design Compiler's advanced compile command enabling retiming, adaptive body biasing, and high-effort optimization for best QoR.
Core Area	The interior region of the chip die where standard cells and macros are placed. Excludes I/O ring and pad frame.
CPF	Common Power Format. Cadence's format (now merged into UPF/IEEE 1801) for specifying multi-voltage power intent.
Crosstalk	Capacitive coupling between adjacent wires. Causes delta delays (aggressor switching affects victim timing) and noise glitches (functional risk on quiet nets).
Decap Cell	Standard-cell-height structure containing a VDD-to-VSS capacitor. Placed in empty areas to reduce dynamic IR drop and supply noise.
Derating	Multiplicative factor applied to cell or wire delays in STA to model OCV. Early path derated by <1.0 (faster), late path by >1.0 (slower).
DEF	Design Exchange Format. Contains physical placement coordinates, routing geometry, and other physical design information for a chip.
Die Area	Total silicon area of the chip including I/O ring, pads, and all structures. Larger than core area.
DRC	Design Rule Check. Verifies layout geometry against foundry manufacturing rules (spacing, width, enclosure, density). Must be clean for tape-out.
DFT	Design for Test. Techniques (scan insertion, BIST, boundary scan) that make the design testable after manufacturing.
ECO	Engineering Change Order. Targeted, minimal netlist or layout change to fix a specific timing, functional, or sign-off issue after implementation.
Elaboration	Synthesis step that parses HDL, resolves hierarchy/parameters, and maps to GTECH (generic technology-independent) primitives.
Electromigration (EM)	Gradual metal atom displacement due to high electron current density. Causes voids (opens) or hillocks (shorts) over time. Characterized by Black's equation.
ERC	Electrical Rule Check. Verifies electrical correctness: floating nodes, improper biasing, ESD violations, latchup risk.
Filler Cells	Cells placed in empty row spaces to maintain N-well continuity, connect power rails, and satisfy metal density rules.
False Path	A timing path that exists in the netlist but is never functionally active. Excluded from STA via set_false_path.
Flyline	Straight-line visual connection between logically connected but physically unrouted pins. Used to assess routing congestion in floorplanning.
Footprint	Physical area occupied by a cell or block on the die, including any keepout regions.
GBA	Graph-Based Analysis. Standard STA mode computing arrival times on the timing graph once. Fast but pessimistic vs Path-Based Analysis (PBA).
GDS II	Graphic Design System II. Binary file format that contains all layout geometry for the chip. Final output sent to the foundry for mask making.
GTECH	Generic Technology. Synopsys internal technology-independent gate library used as intermediate representation during synthesis elaboration.
HVT	High Threshold Voltage cell. Slower than SVT/LVT but has very low leakage power. Used on non-critical paths to minimize standby power.
ICG	Integrated Clock Gating cell. Latch-based AND gate that cleanly gates the clock for power reduction without glitches. Inserted by synthesis tools.
IR Drop	Resistive voltage drop along power distribution network wires (V=IR). Reduces effective VDD at cells, increasing delay.
Jitter	Cycle-to-cycle variation in clock period caused by PLL noise, supply variation, and other sources. Modeled in clock uncertainty.
Latency (Clock)	Total delay from clock source to a flip-flop's clock pin, through all buffers/wires of the clock distribution network.
Legalization	Placement step that moves cells from global placement positions to the nearest legal row-aligned positions with no overlaps.
LEF	Library Exchange Format. Describes the physical abstract views of cells (pin locations, blockages, dimensions) for use by PD tools.
Level Shifter	Cell that converts a signal between two different voltage levels at a power domain boundary. Required for multi-voltage designs.
Liberty (.lib)	Industry-standard format for cell characterization data: timing arcs, power, area, and function at specific PVT conditions.
LVS	Layout vs Schematic. Extracts netlist from layout and compares to reference schematic. Catches opens, shorts, and missing/extra devices.
LVT	Low Threshold Voltage cell. Fastest switching speed, but highest leakage power. Used on critical timing paths to meet WNS.
Macro	Pre-designed hard block (SRAM, ROM, PLL, analog IP) with fixed layout dimensions. Placed early in floorplanning, not synthesized.
Metastability	Condition where a flip-flop output remains at an intermediate voltage indefinitely after setup/hold violation. Resolved by 2-FF synchronizers.
MMMC	Multi-Mode Multi-Corner. STA analysis across all operating modes and PVT corners simultaneously in one tool run.
Multicycle Path	A timing path intentionally designed to take N clock cycles. Declared via set_multicycle_path to relax the timing constraint.
NLDM	Non-Linear Delay Model. 2D cell delay table indexed by input transition time and output load capacitance. Standard model in Liberty files.
OCV	On-Chip Variation. Spatial PVT variation across a single die causing identical cells at different locations to have different delays.
PBA	Path-Based Analysis. Accurate STA mode that re-analyzes specific paths with actual input transitions, removing pessimism vs GBA.
PDN	Power Delivery Network. The complete network of metal rails, rings, stripes, and vias that distributes VDD/VSS to all cells.
POCV	Parametric/Statistical OCV. Most accurate OCV model - each cell delay modeled as a statistical distribution, path slack expressed as sigma confidence.
PrimeTime	Synopsys's industry-standard sign-off STA tool. Uses SPEF parasitics for post-layout timing analysis across MMMC corners.
PVT	Process, Voltage, Temperature. The three main variation sources characterized by IC timing libraries at multiple corners.
QoR	Quality of Results. Overall measure of synthesis/PD success: WNS, TNS, area, power, DRC count, and routability.
Retiming	Synthesis technique that moves registers across combinational logic to balance pipeline stage delays without changing function.
SAIF	Switching Activity Interchange Format. Simulation output capturing signal toggle rates for accurate dynamic power analysis.
SDC	Synopsys Design Constraints. Industry-standard format for timing, area, and power constraints used by all EDA synthesis and STA tools.
Setup Time	Minimum time data must be stable at FF input BEFORE the active clock edge. Violation causes metastability.
Skew	Difference in clock arrival times between any two flip-flops. Target: <50ps local, <200ps global after CTS.
Slack	Timing margin at a path endpoint: Required Time − Arrival Time (setup) or Arrival Time − Required Time (hold). Negative = violation.
Slew Rate	Speed of signal transition (rise/fall time), measured as time to transition between 20%–80% of supply voltage. Slow slew → more delay and power.
SPEF	Standard Parasitic Exchange Format. Contains extracted wire RC values from post-layout extraction for accurate back-annotated STA.
SVT	Standard Threshold Voltage cell. Balanced speed/leakage. General-purpose cell for non-critical paths.
Tap Cell	N-well to VDD and substrate to VSS connection cell. Prevents latchup. Placed at regular intervals (≤50µm) in every standard cell row.
Tempus	Cadence's sign-off STA tool, tightly integrated with Innovus. Supports native MMMC and in-design ECO optimization.
Timing Arc	Delay specification between a cell input and output pin. Includes cell arcs (logic delay), net arcs (wire RC), and constraint arcs (setup/hold).
TNS	Total Negative Slack. Sum of all negative slack values across all timing endpoints. Indicates total timing work remaining.
Uncertainty (Clock)	Timing margin accounting for jitter, skew, and modeling uncertainty. Applied via set_clock_uncertainty in SDC.
UPF	Unified Power Format (IEEE 1801). Standard format for describing multi-voltage power intent: domains, voltages, level shifters, isolation cells.
Utilization	Ratio of placed cell area to total core area, expressed as percentage. Target 60–75% for most designs.
Via	Metal connection between two adjacent metal layers in the layout. Vias have resistance and current capacity limits (EM rules).
WHS	Worst Hold Slack. Most negative hold slack across all endpoints. Must be ≥ 0 at sign-off. Fixed with delay buffer insertion.
WNS	Worst Negative Slack. Most negative setup slack - represents the single worst timing path in the design. Must be ≥ 0 at sign-off.

The Interview Q&A section is what actually got me the offer. The answers here are structured exactly the way senior engineers at Qualcomm want to hear them - not textbook definitions, but practical reasoning. I went through every single Q&A two days before my L2 round and cleared it comfortably.

Priya Krishnamurthy

Physical Design Engineer · MediaTek India, Hyderabad