AHB: The Pipelined Bus
Address and data overlap for higher throughput
AHB, the Advanced High-performance Bus, sits between APB and AXI. It is faster than APB because it pipelines transfers, and it supports bursts. It is a good step up to understand before tackling AXI.
Pipelining: the key idea
APB does address, then data, then the next address, then its data. AHB overlaps them: while the data of one transfer is moving, the address of the next is already being presented. This address phase and data phase pipeline keeps the bus busier and raises throughput without raising the clock speed.
Bursts
AHB can issue a burst: a sequence of related transfers to incrementing addresses announced up front, so the slave knows more is coming and can prepare. Bursts are far more efficient than many separate single transfers for moving blocks of data like cache lines.
| Signal | Meaning |
|---|---|
| HADDR / HWRITE | Address and direction |
| HTRANS | Transfer type (idle, busy, nonseq, seq) |
| HBURST | Burst length and type |
| HSIZE | Transfer width |
| HWDATA / HRDATA | Write data / read data |
| HREADY | Slave ready / pipeline advance |
| HRESP | Response (okay or error) |
HREADY is central: it both signals the slave is done and advances the pipeline, so a slow slave inserting wait states stalls the whole pipeline cleanly.
because address and data phases overlap, the data on the bus belongs to the previous address, not the one currently on HADDR. Lining up which data goes with which address is the classic point of confusion in AHB. Track the pipeline by phase, not by clock cycle.
summarize the AMBA ladder in one line: APB is simple and unpipelined for slow peripherals, AHB is pipelined with bursts for higher throughput, AXI is fully channelized for maximum performance. Interviewers love that progression.