AXI: The High-Performance Interface
Five independent channels for maximum throughput
AXI, the Advanced eXtensible Interface, is the high-performance AMBA protocol and the one you will be asked about most. It reaches high throughput by splitting a transaction into five independent channels, each using the VALID/READY handshake you already know.
The five channels
| Channel | Direction | Carries |
|---|---|---|
| Write Address (AW) | Master to slave | Address and control for a write |
| Write Data (W) | Master to slave | The write data (can be a burst) |
| Write Response (B) | Slave to master | Okay or error after the write |
| Read Address (AR) | Master to slave | Address and control for a read |
| Read Data (R) | Slave to master | The read data (can be a burst) |
Address and data are on separate channels, so the master can send a write address while previous write data is still flowing. Reads and writes use entirely separate channels, so they can happen at the same time.
Every channel is a VALID/READY handshake
Each of the five channels transfers exactly the way you learned: the source raises VALID, the destination raises READY, and the beat moves when both are high. Learn the handshake once and you understand flow control on all five channels.
What makes AXI fast
- Independent read and write channels: reads and writes proceed in parallel.
- Bursts: one address launches many data beats.
- Multiple outstanding transactions: the master can issue several requests before any complete.
- Out-of-order completion: transactions carry an ID, so a slave may return responses in a different order, and the master matches them by ID.
Burst types and AXI4 specifics
A burst is described by a start address, a length (number of beats), a size (bytes per beat), and a burst type that says how the address moves from beat to beat:
| Burst type | Address behaviour | Typical use |
|---|---|---|
| FIXED | Same address every beat | Reading or writing one FIFO or peripheral register repeatedly |
| INCR | Increments by the transfer size each beat | Normal memory access (the common case) |
| WRAP | Increments, then wraps at a boundary | Cache-line fills that start at the critical word |
AXI4, the version you will meet most, extends the older AXI3 in a few ways worth knowing: an INCR burst can be up to 256 beats (AXI3 allowed 16), write-data interleaving was removed to keep slaves simple, the separate write-data ID (WID) was dropped, and QoS and region signals were added. The five-channel VALID/READY core is identical, so everything above still applies.
AXI-Lite
There is a stripped-down version, AXI-Lite, with no bursts and one transfer at a time. It keeps the five-channel structure but is far simpler, and it is the usual choice for register interfaces where full AXI would be overkill.
the senior-level summary: AXI gets its performance from five independent channels, separate read and write paths, bursts, and multiple outstanding, ID-tagged transactions that can complete out of order. Each channel is just VALID/READY. Say that and you have covered what most AXI interview questions are really asking.
the write response (B) channel exists for a reason: a write is not complete until the master receives the response. Assuming a write is done the moment the data is sent is a common mistake. Always wait for B.