Module 28 min

The VALID/READY Handshake

The one idea behind every modern on-chip bus

Before any specific bus, learn this one mechanism. The VALID/READY handshake is how nearly every modern on-chip interface, including AXI, moves a piece of information from a sender to a receiver. Understand it once and the rest is detail.

Two signals, one rule

The sender drives VALID when it has data to offer. The receiver drives READY when it is able to accept. The transfer happens on the clock edge where both VALID and READY are high at the same time. That is the entire mechanism.

verilog
// A transfer occurs on any rising clock edge where
// both sides agree:
wire transfer = valid && ready;

always @(posedge clk)
  if (transfer)
    data_captured <= data;  // sender's data is taken

Why it is so useful

  • Either side can stall: a slow sender just keeps VALID low, a busy receiver keeps READY low. No data is lost.
  • It needs no fixed timing agreement, only the shared rule, so fast and slow blocks interoperate.
  • It is the same pattern on every AXI channel, so once you know it you know AXI flow control.

The rules that prevent deadlock

  1. Once the sender asserts VALID, it must keep VALID high and the data stable until the transfer happens. It may not withdraw an offer.
  2. The sender must not wait for READY before asserting VALID. VALID must not depend on READY, or both sides could wait forever.
  3. The receiver may assert READY whenever it likes, before or after VALID.
Watch out

the classic deadlock bug is making VALID depend on READY (the sender only offers data once it sees the receiver is ready). If the receiver only becomes ready once it sees valid data, neither moves. The rule VALID must not wait for READY exists precisely to stop this.

Pro tip

in an interview, draw two signals and say: transfer happens when VALID and READY are both high on a clock edge; VALID cannot wait for READY. That sentence shows you understand AXI flow control at its core.