APB: The Simple Peripheral Bus
The easy AMBA bus for slow peripherals
APB, the Advanced Peripheral Bus, is the simplest member of the AMBA family. It is built for low-bandwidth peripherals like timers, GPIO, and control registers, where simplicity matters more than speed. Start here because its two-phase transfer is easy to picture.
When APB is used
APB is not pipelined and moves one transfer at a time, so it is slow by design. That is exactly what you want for configuration registers and simple peripherals: minimal logic, low power, easy to implement. A faster bus usually bridges down to an APB segment for these slow devices.
The two phases
Every APB transfer has two phases driven by the clock:
- Setup phase: the master drives the address, write signal, and (for a write) data, and asserts PSEL to select the peripheral. PENABLE is low.
- Access phase: the master asserts PENABLE. The transfer completes when the slave asserts PREADY. For a read, the slave drives the data here.
| Signal | Meaning |
|---|---|
| PSEL | Selects this peripheral |
| PENABLE | Marks the access phase |
| PADDR / PWRITE | Address and read/write direction |
| PWDATA / PRDATA | Write data / read data |
| PREADY | Slave is done (can extend the transfer) |
| PSLVERR | Optional error response |
A slow slave holds PREADY low to stretch the access phase until it is ready, which is how APB adds wait states.
remember APB as setup then access, one transfer at a time. If asked where it is used, say configuration and control registers and slow peripherals, reached through a bridge from a faster bus.