APB: The Simple Peripheral Bus

APB, the Advanced Peripheral Bus, is the simplest member of the AMBA family. It is built for low-bandwidth peripherals like timers, GPIO, and control registers, where simplicity matters more than speed. Start here because its two-phase transfer is easy to picture.

When APB is used

APB is not pipelined and moves one transfer at a time, so it is slow by design. That is exactly what you want for configuration registers and simple peripherals: minimal logic, low power, easy to implement. A faster bus usually bridges down to an APB segment for these slow devices.

The two phases

Every APB transfer has two phases driven by the clock:

1. Setup phase: the master drives the address, write signal, and (for a write) data, and asserts PSEL to select the peripheral. PENABLE is low.
2. Access phase: the master asserts PENABLE. The transfer completes when the slave asserts PREADY. For a read, the slave drives the data here.

On a clock it is easy to picture. A write with no wait states takes two cycles: in the setup cycle the master drives PADDR, PWDATA, PWRITE and PSEL; in the access cycle it also asserts PENABLE, and the slave captures the data on the edge where PREADY is high. A read has the same shape, except the slave drives PRDATA during the access phase and the master samples it when PREADY is high. If the slave needs more time it just keeps PREADY low, adding one wait-state cycle each time.

A slow slave holds PREADY low to stretch the access phase until it is ready, which is how APB adds wait states.