Role track

Become a design verification engineer

DV engineers prove a design works before it becomes silicon. They build testbenches, write constrained-random stimulus and assertions, and measure coverage until the bugs run out. This track goes from digital logic to UVM.

7
free paths
69
lessons
~9 h
of reading

Foundations

  1. Digital ElectronicsThe logic you will be verifying.11 lessons · Beginner
  2. VerilogRead and write the RTL under test.14 lessons · Beginner

Verification

  1. Design VerificationTestbenches, SystemVerilog, UVM, coverage and SVA.14 lessons · Beginner
  2. Hardware ProtocolsAXI, APB, SPI, I2C and UART: what most testbenches drive.8 lessons · Intermediate
  3. Clock Domain CrossingCDC bugs are among the hardest to find in simulation.8 lessons · Intermediate

Tools

  1. Linux for VLSIRegressions run on Linux farms.7 lessons · Beginner
  2. TCL for EDAScripting for tool flows and reports.7 lessons · Beginner

Get hired

  1. 08VLSI domains: which one is for you?How DV compares with design and PD roles.Free
  2. 09Interview BootcampOptional: RTL questions and company-wise interview prep.Course · ₹299
  3. 10A mock interviewOptional: practise answering out loud.Free