Role track

Become a physical design engineer

PD engineers turn a synthesized netlist into a chip the foundry can build: floorplan, placement, clock tree, routing and signoff. This track takes you there in the order the work actually happens.

9
free paths
102
lessons
~14 h
of reading

Foundations

  1. Digital ElectronicsFlip-flops, setup and hold, and the logic every cell implements.11 lessons · Beginner
  2. VerilogEnough RTL to read what synthesis hands you.14 lessons · Beginner

The flow

  1. SynthesisWhere your netlist and SDC come from, and what QoR means.11 lessons · Beginner
  2. Static Timing AnalysisThe language of timing closure, used every day in PD.16 lessons · Intermediate
  3. Physical DesignThe core of the job, floorplan to ECO.11 lessons · Intermediate
  4. Physical VerificationDRC, LVS and antenna: the last gate before tape-out.12 lessons · Intermediate
  5. Low Power Design & UPFPower domains, level shifters and UPF on modern SoCs.13 lessons · Advanced

Tools

  1. Linux for VLSIEvery EDA tool runs on Linux.7 lessons · Beginner
  2. TCL for EDAScripts drive ICC2, Innovus and PrimeTime.7 lessons · Beginner

Practise

  1. 10Lab: the router reports 18.4% overflowFind the placement cause of a congestion hot spot.Engineering Lab
  2. 11Lab: CTS leaves 87 ps of clock skewBalance a clock tree and use skew on purpose.Engineering Lab
  3. 12Lab: 326 hold violations after routingClose hold without breaking setup.Engineering Lab
  4. 13OpenLane RTL-to-GDSOptional: run the whole flow yourself on a RISC-V CPU, with a certificate.Course · ₹999

Get hired

  1. 14Physical design interview questionsThe questions PD rounds ask most.Free
  2. 15128 STA interview questionsEvery PD interview includes timing.Free
  3. 16A mock interviewOptional: practise with a working PD engineer.Free