Module 21 min

VLSI Domains - Which One Is For You?

What you do: Write synthesizable Verilog/SystemVerilog. Design microarchitecture - FSMs, pipelines, datapaths. Write verification plans.

RTL Design Engineer

What you do: Write synthesizable Verilog/SystemVerilog. Design microarchitecture - FSMs, pipelines, datapaths. Write verification plans.

Skills needed: SystemVerilog, microarch, timing-aware RTL coding.

Companies: Intel, AMD, ARM, Qualcomm, Apple, NVIDIA (design teams).

Synthesis Engineer

What you do: Run synthesis flows (DC/Genus), meet QoR targets, write SDC constraints, perform timing closure at gate level.

Skills needed: TCL scripting, DC/Genus, SDC, timing analysis, QoR optimization.

Companies: Samsung, MediaTek, Marvell, Broadcom.

Physical Design Engineer

What you do: Floorplan, power plan, place, CTS, route, close timing post-route. Work in Innovus or ICC2 daily.

Skills needed: Innovus/ICC2, floorplanning, CTS, routing DRC, ECO.

Companies: TSMC, GlobalFoundries, fabless design houses, Apple silicon.

STA Engineer

What you do: Sign-off timing across all MMMC corners using PrimeTime/Tempus. Write ECO scripts. Own WNS/TNS/WHS closure.

Skills needed: PrimeTime, SPEF, MMMC, OCV/AOCV, ECO flows.

Companies: Any semiconductor company with tape-out responsibility.

Physical Verification Engineer

What you do: Run DRC, LVS, ERC, Antenna checks. Debug violations. Own Calibre flow. Coordinate tape-out sign-off.

Skills needed: Calibre DRC/LVS, SVRF rule decks, GDS debugging, Calibre xRC.

Companies: Foundry customers, TSMC design enablement, IP companies.

Verification Engineer (DV)

What you do: Write UVM testbenches, functional coverage, formal verification, emulation. Ensure RTL is functionally correct.

Skills needed: SystemVerilog, UVM, SVA, Questa/VCS, formal tools.

Companies: All major semiconductor companies.