Module 43 min

Essential Tools - What to Learn and How

OpenLane Quick Start - Full RTL-to-GDS in One Command

Pro Tip

Reality Check — Industry EDA tools (DC, Innovus, PrimeTime, Calibre) are expensive and require a license. As a student, use the free alternatives below to build hands-on experience. Hiring managers know you won't have industry tool access - they want to see that you understand the concepts and can demonstrate hands-on work with open-source equivalents.

Domain	Industry Tool	Free/Open Alternative	How to Practice
Synthesis	Synopsys DC / Cadence Genus	Yosys (open source)	Synthesize your Verilog designs with Yosys. Understand liberty files. Write SDC constraints manually. Compare area reports.
Place & Route	Cadence Innovus / Synopsys ICC2	OpenROAD via OpenLane2	Use OpenLane with Sky130 PDK. Run full RTL-to-GDS on a small design (UART, I2C, simple CPU). Examine each output.
STA	Synopsys PrimeTime / Cadence Tempus	OpenSTA (inside OpenLane)	Read timing reports from OpenSTA. Understand slack calculation. Introduce timing violations manually and fix them.
Simulation	Synopsys VCS / Cadence Questa	Verilator / Icarus Verilog	Write testbenches. Simulate your RTL. View waveforms in GTKWave. Practice writing self-checking testbenches.
Physical Verification	Calibre DRC/LVS	Magic VLSI / KLayout	Open Sky130 GDS in KLayout. Inspect metal layers. Run built-in DRC checks. Understand what each layer represents.
Parasitic Extraction	Calibre xRC / Synopsys StarRC	OpenRCX (inside OpenROAD)	Run OpenRCX on a placed-and-routed design. Examine the SPEF output. Understand how RC values affect timing.
Waveform Viewing	Synopsys DVE / Cadence SimVision	GTKWave	View VCD dumps from Verilator/Icarus simulation. Practice reading waveforms, adding cursors, measuring timing.
Layout Editing	Cadence Virtuoso / Synopsys L-Edit	Magic VLSI / KLayout	Draw simple standard cells in Magic. Understand how transistors form. See the connection between schematic and layout.

OpenLane Quick Start - Full RTL-to-GDS in One Command

SHELL - OpenLane2 with Sky130 PDK

# Install OpenLane2 (requires Docker or Nix)
pip install openlane

# Create a minimal design config
mkdir my_design && cd my_design
cat > config.json << 'EOF'
{
  "DESIGN_NAME": "my_alu",
  "VERILOG_FILES": "src/alu.v",
  "CLOCK_PORT": "clk",
  "CLOCK_PERIOD": 10,
  "FP_CORE_UTIL": 40,
  "PL_TARGET_DENSITY": 0.4
}
EOF

# Run complete RTL-to-GDS flow
openlane config.json

# Outputs you'll find in runs/RUN_*/:
# synthesis/    → gate-level netlist (.v)
# floorplan/    → DEF with core/IO defined
# placement/    → placed cells DEF
# cts/          → clock tree built DEF
# routing/      → fully routed DEF + GDS
# signoff/      → timing reports (OpenSTA)
# signoff/      → DRC results (KLayout/Magic)

# View final GDS in KLayout:
klayout runs/RUN_latest/final/gds/my_alu.gds