Module 31 minLearning Roadmap - Fresher to ProfessionalLearning Roadmap - Fresher to ProfessionalEnlarge PHASE 1 - FOUNDATION Months 0–6 Digital Electronics Basics Logic gates, FFs, timing, FSMs Verilog / SystemVerilog RTL coding, simulation basics CMOS Fundamentals Transistors, gates, delay, power Linux + TCL Scripting Shell, grep, awk, TCL loops Computer Architecture Pipeline, cache, memory hierarchy Resources: Weste & Harris CMOS VLSI Design, Patterson & Hennessy Comp Arch PHASE 2 - CORE VLSI Months 6–18 Logic Synthesis Deep Dive DC, SDC constraints, QoR Static Timing Analysis Setup/hold, paths, PrimeTime Physical Design Fundamentals Floorplan, place, CTS, route Physical Verification Basics DRC, LVS, Calibre concepts OpenLane / Free PDK Practice Sky130 - full flow hands-on Resources: Rabaey CMOS, Bhatnagar ASIC Design, Synopsys/Cadence tutorials PHASE 3 - PROFESSIONAL Year 1–3 MMMC + OCV/AOCV Mastery Full sign-off corner analysis Advanced CTS Optimization Skew groups, useful skew, ccopt Low-Power Design (UPF) Multi-Vt, power domains, CPF Timing Closure ECO Flow PT-ECO, post-route, fill-aware Tape-out Ownership Sign-off checklist, tapeout flow Resources: Company flows, Synopsys/Cadence training, internal project experience PHASE 4 - EXPERT Year 3+ Advanced Node PDK (3nm/5nm) FinFET, GAA, double-patterning EDA Tool Development OpenROAD, Python EDA scripting Methodology Ownership Define flows for whole team/project Research / Advanced Topics POCV, ML-assisted PD, 3D-IC Technical Leadership Staff/Principal Engineer role Resources: IEEE TCAD, DAC/ICCAD papers, internal tapeout retrospectives Click to enlargeMark Complete← VLSI Domains - Which One Is For You?Essential Tools - What to Learn and How →