Module 62 min

What Interviewers Actually Evaluate

Common Mistakes That Fail Candidates

  • Can explain why, not just what - "Why does hold analysis use the fast corner?" shows deep understanding.
  • Hands-on experience - even with open-source tools. Running OpenLane end-to-end beats "I studied PD in class."
  • Correct use of units and numbers. "Skew under 50ps," not "skew should be small."
  • Knows limits and tradeoffs. "Increasing drive strength fixes setup but increases power and may cause hold violations."
  • Asks clarifying questions before answering - demonstrates engineering mindset.
  • Admits uncertainty honestly: "I haven't used Genus directly but DC concepts are the same - let me explain my DC knowledge."
  • Connects concepts: "DRC-clean layout is needed before Calibre xRC extraction which feeds sign-off STA."

Common Mistakes That Fail Candidates

  • Memorizing answers without understanding. Interviewers probe with follow-up questions - memorized answers collapse immediately.
  • "I know the theory but haven't used the tools." Every VLSI job requires tool proficiency. Use open-source tools to fill this gap.
  • Getting confused between setup and hold. This is the most basic STA concept - if you mix them up, the interview ends.
  • Not knowing which corner is used for setup vs hold analysis. This comes up in almost every STA interview.
  • Saying "I would just rerun synthesis" to fix a post-route timing violation. Late-stage fixes must be ECO-based - no full rerun.
  • Cannot explain what SPEF is and why it's needed. This is fundamental to any STA sign-off conversation.
  • Treating LVS-clean as the same as functionally correct. Interviewers know this is a common misconception.
Pro Tip

The Most Common Interview Question - And How to Answer It Properly — "Explain setup and hold time." - Almost every VLSI interview starts here. Wrong answer: "Setup is the time before clock, hold is the time after clock." Right answer: "Setup time is the minimum duration that data must be stable at the flip-flop input before the active clock edge, so the FF can reliably capture it. Hold time is the minimum duration data must remain stable after the clock edge. Violating setup causes data to arrive late - the FF may not capture the correct value. Violating hold causes data to change too quickly - the FF may capture the new value instead of the intended one. Critically, hold violations cause failures at all frequencies, not just high speed - they're structural, not a speed problem. That's why they're fixed with delay buffer insertion rather than clock frequency reduction."