Module 85 min
A Day in the Life - By Role
Physical Design Engineer - Typical Day (Pre-Tapeout)
PD Engineer
Physical Design Engineer - Typical Day (Pre-Tapeout)
| Time | Activity | Tools Used |
|---|---|---|
| 9:00 AM | Check overnight Innovus place-and-route run results. Review DRC violation count trend and timing summary. | Innovus GUI, log parser scripts |
| 9:30 AM | Team stand-up: report WNS/TNS status, blocking issues (congested area, unresolvable DRC in macro boundary) | Confluence, Jira |
| 10:00 AM | Debug 3 specific DRC violations near a macro corner that have resisted automatic fixing. Manually re-route 2 wires. | Innovus ECO route, DRC GUI |
| 11:30 AM | Review CTS results. Skew is 220ps - above 200ps target. Adjust ccopt settings, re-run CTS on critical clock domain. | Innovus ccopt_design |
| 1:30 PM | Run post-route STA to check setup/hold after morning ECO changes. Two new hold violations introduced by yesterday's buffer insertion. | Tempus, timing reports |
| 2:30 PM | Fix hold violations by inserting delay buffers on 2 short paths. Re-run route_opt for those nets. | Innovus ecoAddDelay |
| 3:30 PM | Meeting with STA team to align on acceptable WNS margin at this stage of the project. | – |
| 4:00 PM | Write TCL script to automate tomorrow's overnight run: place → CTS → route → extractRC → STA → DRC. Submit to compute farm. | TCL, LSF job scheduler |
| 5:00 PM | Update project tracking spreadsheet. Document today's changes. Review tomorrow's schedule. | Excel, Confluence |
STA Engineer
STA Engineer - Typical Day (Sign-off Phase)
| Time | Activity | Tools Used |
|---|---|---|
| 9:00 AM | Review overnight PT sign-off results across 5 MMMC corners. Identify which corners still have violations. | PrimeTime, report parser |
| 9:45 AM | WNS is -0.04ns at func_slow corner on one clock domain. Identify the critical path - reg-to-reg through a wide adder. | PT report_timing |
| 10:15 AM | Run PT-ECO to generate fix suggestions (upsize 3 cells, insert 1 buffer). Review suggestions for reasonableness. | PT fix_eco_timing |
| 10:45 AM | Send ECO script to PD team for implementation in Innovus. Coordinate on expected turnaround. | Email, Jira ticket |
| 11:30 AM | Review hold corner (func_fast) - clean. Review scan corner (scan_slow) - 2 violations. Update tracking spreadsheet. | PrimeTime, Excel |
| 1:30 PM | New SPEF delivered from PD team after yesterday's route ECO. Run full PT update on all 5 corners. ~2 hour runtime. | PrimeTime update_timing |
| 3:30 PM | Results back: func_slow now +0.02ns (CLEAN). Scan corner improved to -0.01ns - one path remains. Document. | PrimeTime, Confluence |
| 4:00 PM | Debug the remaining scan violation - it's an MCP (multicycle_path) that has wrong hold correction. Fix SDC, re-run. | PrimeTime, SDC editor |
| 5:00 PM | Submit final overnight run with updated SDC. Send status email to project lead: "func_slow CLEAN, scan_slow -0.01ns in progress" | LSF, email |
PV Engineer
Physical Verification Engineer - Typical Day (Pre-Tapeout)
| Time | Activity | Tools Used |
|---|---|---|
| 9:00 AM | Review overnight Calibre DRC results. 142 violations remain (down from 2,400 last week). Classify by rule. | Calibre RVE, shell scripts |
| 9:30 AM | Top rule: M3_SPACING.2 - 47 violations, all in one macro boundary region. Root cause: macro halo not set correctly. | Calibre RVE, Innovus |
| 10:00 AM | Fix: Adjust macro halo in Innovus, re-run routing around that macro. Generates new GDS for next DRC run. | Innovus, script |
| 11:00 AM | LVS run completed overnight - 3 opens found. Debug: all 3 are on VDD tie-off cells that weren't properly connected after fill insertion. | Calibre RVS, layout viewer |
| 11:45 AM | Fix: Add missing metal connections in Innovus. Verify fix with quick LVS on the affected nets only. | Innovus ECO, Calibre partial LVS |
| 1:30 PM | Antenna check: 8 violations remain. All on NAND gate inputs with long M1 wires. Add jumper vias to M3 for 6 of them; insert 2 antenna diodes for the others. | Innovus antenna fixer, Calibre |
| 3:00 PM | Submit full DRC/LVS/Antenna run to compute farm with new GDS. Expected 4 hours runtime. | LSF compute farm |
| 3:30 PM | Prepare tape-out checklist. Verify all IP blocks have current DRC waivers. Coordinate with fab liaison on GDS delivery window. | Confluence checklist, email |
| 5:00 PM | Update PV sign-off dashboard. Send status: "DRC: 142→TBD tonight, LVS: 3 opens fixed, Antenna: 8→2 fixes sent to PD" | Dashboard, email |
Synthesis Eng
Synthesis Engineer - Typical Day (Synthesis Closure)
| Time | Activity | Tools Used |
|---|---|---|
| 9:00 AM | Review overnight compile_ultra run. WNS = -0.28ns, TNS = -15.4ns. 47 violating endpoints. Area 4.2 mm². | DC, QoR scripts |
| 9:30 AM | Identify top 5 violating paths - all through the FP multiply unit. Discuss with RTL team: can MCP be applied? | DC report_timing, email |
| 10:00 AM | RTL team confirms multiplier is 2-cycle. Add MCP to SDC. Re-run compile_ultra incremental on that path group. | DC compile -incremental |
| 11:00 AM | New WNS = -0.06ns, TNS = -0.9ns. Good progress. Remaining violations are in the interconnect arbiter. | DC, report_qor |
| 1:30 PM | Try path group with higher weight on the arbiter timing paths. Also try ungroup on the arbiter sub-module to allow cross-boundary optimization. | DC group_path, ungroup |
| 2:30 PM | Check max-cap violations - 12 found on high-fanout reset net. Set don't_touch on clock buffers. Insert buffer tree on reset. | DC set_max_fanout, compile |
| 3:30 PM | Run power analysis with SAIF from simulation. Dynamic power = 380mW - 15% over target. Apply clock gating and increase HVT cell usage on non-critical paths. | DC, power_compiler |
| 4:30 PM | Submit overnight full compile_ultra run with updated SDC and power optimizations. Write synthesis run notes for the team. | LSF, Confluence |
| 5:00 PM | Write handoff email to PD team with current netlist, mapped SDC, and QoR summary noting areas of concern for floorplanning. |